1. Field of the Invention
The present invention relates to a head substrate, printhead, head cartridge, and printing apparatus. Particularly, the present invention relates to a head substrate prepared by forming, on the same substrate, an electrothermal transducer for generating heat energy necessary to print, and a driver circuit for driving the electrothermal transducer, a printhead using the head substrate, a head cartridge using the printhead, and a printing apparatus.
2. Description of the Related Art
The electrothermal transducers (heaters) and driver circuits of a printhead mounted in a conventional inkjet printing apparatus are formed on the same substrate by a semiconductor process technique as disclosed in, for example, U.S. Pat. No. 6,290,334. There has already been proposed a substrate on which an ink supply channel for supplying ink is arranged on the substrate and heaters are arrayed at positions opposite to each other near the ink supply channel.
FIG. 10 is a view showing the layout of a head substrate used in a conventional inkjet printhead.
In FIG. 10, a substrate 100 is formed by integrating, by a semiconductor process technique, heaters and driver circuits for driving them. Each heater array 101a is an array of heaters. Each driver array (driving element array) 101b is an array of driver transistors (driving elements) for switching between supplying a desired current and not supplying the current to heaters. An ink supply channel 102 supplies ink from the back surface of the substrate. Each shift register (S/R) 103 temporarily stores print data. Each latch circuit 104 latches print data stored in the corresponding shift register (S/R) 103 at once. Each decoder 105 selects a desired heater block of the heater array 101a in unit of concurrently drivable block so as to drive it. Each input circuit block 106 includes a buffer circuit for inputting digital signals to the shift register 103 and decoder 105. Signal lines 107 transmit signals from the shift register 103 and decoder 105 to select individual segments in the heater array 101a and driver array 101b. 
Each converter array 108 is an array of level converters which convert, into driving voltages to be applied to the gates of the driver transistors, the amplitude voltages of output signal pulses, from the shift register 103 and decoder 105, that are transferred via the signal lines 107. Each converted voltage generation circuit 109 generates a driving voltage for the level converters of the converter array 108. Each contact pad 110 is used to input/output an electrical signal from/to outside the substrate.
FIG. 11 is a circuit diagram showing an equivalent circuit corresponding to one segment (one heater) of the heater array 101a and driver array 101b which are integrated on the head substrate shown in FIG. 10 and drive heaters for discharging ink.
In FIG. 11, an AND circuit 201 calculates the logical product of two input signals. The AND circuit 201 receives a block selection signal which is sent from the decoder 105 to select heaters of each block, and a print data signal which is transferred to the shift register 103 and latched by the latch circuit 104. Based on the logical product, each segment can be selectively turned on. An inverter circuit 202 buffers an output from the AND circuit 201. A VDD power supply line 203 serves as the power supply of the inverter circuit 202. An inverter circuit 204 buffers an output from the inverter circuit 202. A VH power supply line 205 is used for supplying a voltage to be applied to a heater. A driver transistor 207 serves as a switching element for switching between supplying a current and not supplying the current, to a heater 206. A VHTM power supply line 208 serves as a power supply for supplying power to the inverter circuit 204 functioning as a buffer, thereby applying a gate voltage to the driver transistor 207.
A current flowing through the heater 206 is fed back to a ground line (GNDH) 209. A level converter 210 is made up of a plurality of inverter circuits 204, and converts the amplitude voltage of an output pulse from the AND circuit 201 into the gate driving voltage of the driver transistor. A VSS voltage line 211 provides the GND potential of the inverter circuits 202 and 204.
A circuit (to be referred to as a converted voltage generator hereinafter) 220 corresponds to one segment of the converted voltage generation circuit 109 which internally converts a voltage (VHT voltage) of a VHT power supply line into a voltage VHTM for driving the driver transistor 207.
A VHT power supply line 223 supplies a voltage which is the source of the VHTM voltage in the converted voltage generator 220. A MOSFET transistor 222 serves as a buffer for output. Dividing resistors 221a and 221b determine the gate voltage of the MOSFET transistor 222. A load resistor 225 is connected to the source of the MOSFET transistor 222.
The voltage VHTM is desirably adjusted to make the ON resistance of the driver transistor 207 sufficiently low. The voltage VHTM is set higher than the VDD voltage, and lower than the tolerable voltage of the element of the level converter 210. More specifically, the converted voltage generator 220 employs a so-called source follower arrangement. The value of the converted voltage (voltage VHTM) is determined by applying a predetermined reference voltage to the gate of the MOSFET transistor 222. In this circuit arrangement, by always applying a predetermined voltage to the gate of the MOSFET transistor 222, the converted potential hardly varies even by a current flowing through the drain-source path.
FIG. 12 is an equivalent circuit diagram of a circuit corresponding to one bit of the shift register 103 and latch circuit 104 which temporarily store print data.
In FIG. 12, print data DATA is input to the shift register in synchronism with a clock CLK, and the input print data is latched in synchronism with a latch signal LT. When a heat enable signal HE is input, a print data signal is output from the latch circuit to the AND circuit 201 while the heat enable signal is enabled.
FIG. 13 is a timing chart for explaining a series of operations from receiving print data in the shift register 103 to driving the heater 206 by supplying a current to it.
In FIG. 13, print data is supplied to a data pad (not shown) in synchronism with the clock CLK input to a clock pad (not shown). The shift register 103 temporarily stores the print data. The latch circuit 104 latches the print data in synchronism with the latch signal LT supplied to a latch pad (not shown). Then, the logical product of a block selection signal for selecting heaters of a desired block, and a print data signal output in accordance with the latch signal LT is calculated. A heater current (current VH) flows in synchronism with the heat enable signal HE, which directly determines a current driving time, and the logical product.
Printing is performed by repeating the series of operations for respective blocks.
FIG. 14 is a view showing connection of power supply wiring lines in the head substrate shown in FIG. 10.
In FIG. 14, power supply pads VH 130, 132, 134, and 136 supply voltages to be applied to heaters. Ground pads GND 131, 133, 135, and 137 correspond to the power supply pads. Wiring lines 140 are divided to independently supply power from the power supply pads VH to respective blocks. Wiring lines 141 are divided to feed back power from the blocks to the ground pads GND. These wiring lines will be called VH power supply wiring lines and GND wiring lines.
Segments including heaters arranged on the head substrate are divided into 16 groups A to P. Power is independently supplied and fed back to and from each group in order to keep power loss constant by making uniform the wiring resistances of the VH power supply wiring lines and GND wiring lines which are connected to the respective groups. The widths of the wiring lines are adjusted to have the same resistance value. Each group is comprised of segments (including heaters), respectively belonging to different time-divisionally driven blocks.
FIG. 15 is a layout view showing connection of power supply wiring lines in the head substrate shown in FIG. 14.
In FIG. 15, reference numeral 171 denotes a heater; and 172, a MOSFET which is a driver transistor corresponding to one heater. Reference numeral 175 denotes a drain electrode of the MOSFET 172 series-connected to the heater 171; 177, a gate electrode of the MOSFET 172; and 176, a source electrode of the MOSFET 172.
Segments corresponding to heaters are divided into groups 170. A current is independently supplied and fed back to and from each group.
VH power supply wiring lines 180a to 180c supply power to respective groups. Currents supplied from the VH power supply wiring lines are fed back through GND wiring lines 181a to 181c. The VH power supply wiring lines 180a to 180c and GND wiring lines 181a to 181c are divided to independently supply the VH power and ground to respective groups. The widths of the wiring lines are adjusted to have the same resistance value.
In FIG. 15, the VH power supply wiring lines are laid out above heaters for descriptive convenience. The wiring lines may also be three-dimensionally formed on driver transistors by a multi-layer wiring technique.
However, according to the power supply wiring connection as shown in FIG. 14, the wiring becomes longer as the longer side of the chip (head substrate) becomes longer. In addition, as the group division count increases, the widths of wiring lines independently connected to respective groups become narrower, and the wiring resistance tends to rise as a whole. The increase in wiring resistance causes so-called power loss because power, which should be originally consumed by heaters, is consumed by the wiring to a certain degree. If the original power supply voltage is increased to compensate for the power loss, this adversely affects the durable service life of heaters. Further, heat generated by power consumption by the wiring raises the temperature of the printhead itself, adversely affecting the ink discharge characteristic.
If the width of the power wiring is made wider to decrease the resistance value of the wiring, the layout efficiency decreases, the chip area increases, and the printhead cost rises.